The present invention is directed, in general, to a non-contact method for determining the quality of a dielectric and, more specifically, to a non-contact method for determining soft breakdown in a dielectric.
The use of different methods for manufacturing semiconductors has reached phenomenal proportions over the last decade. Equally phenomenal has been the ever-decreasing device size of the semiconductors themselves, including the thickness of dielectrics such as gate oxides, within metal-oxide semiconductor field effect transistors (MOSFETs). It is particularly desirable to make the thickness of the gate oxide in these devices as small as possible since the drive current in semiconductor devices increases as the thickness of the gate oxide decreases. Unfortunately, along with the trend towards thinner gate oxides comes the increased risk of reduced quality of the dielectric gate oxide layers. Moreover, at present day ultra-thin thicknesses, it is imperative that the gate oxide be of the highest quality possible.
To assist in determining the quality of gate oxides, as well as other dielectrics, several techniques have been developed. Among these techniques are xe2x80x9ccontactxe2x80x9d and xe2x80x9cnon-contactxe2x80x9d techniques, both of which may be used to measure a variety of charge-trapping parameters of dielectrics, such as charge contamination (Qm), the degree of density of interface traps (Dit), the flatband voltage (Vfb) and the level of mobile charge carrier, to determine the quality of the dielectric. Those skilled in the art are familiar with such contact techniques, such as capacitance-voltage testing (C-V testing) and the difficulties, time and costs associated with such techniques.
Recently, non-contact techniques have been developed to overcome the numerous deficiencies of contact techniques. One such non-contact technique is the corona-oxide-semiconductor testing (COS testing) process that allows the quality of a dielectric to be determined without physically contacting the semiconductor wafer in the process. Advantages associated with non-contact techniques include the fact that they are less invasive, as well as quicker, in determining gate oxide quality. In addition, some non-contact techniques, such as COS testing, allow gate oxide quality to be determined xe2x80x9cin-linexe2x80x9d, during the manufacturing process, rather than after manufacturing of the complete semiconductor device has been completed. Unfortunately, although COS testing is one of the common non-contact techniques currently used for determining gate oxide quality, it remains dependent on the use of the charge-trapping parameters discussed above.
While the commonly used charge-trapping parameters of dielectrics (Qm, Dit, Vfb) are helpful in determining gate oxide quality, they may not be the best indicators of the gate oxide""s quality. Thus, in light of this limitation, accuracy provided by the charge-trapping parameters, techniques for determining dielectric layer quality that rely on these parameters are likewise limited in accuracy when determining the quality of dielectrics.
Accordingly, what is needed in the art is an improved non-contact technique for determining the quality of dielectrics, such as gate oxides, in a semiconductor device that does not suffer from the deficiencies of the techniques found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a non-contact method for determining a quality of a semiconductor dielectric. In one advantageous embodiment, the method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining soft breakdown of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, in one embodiment, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1.2 nm or applying 16 megavolts when the thickness is about 5.0 nm.
The method may also include determining a stress-induced leakage current within the dielectric from the voltage drop as a function of time. The stress-induced leakage current can be determined from the same data from which the soft breakdown is determined. Typically, however, the stress-induced leakage current will be determined over a longer period of time than that used to determine the soft breakdown.
Because of the ease with which the soft breakdown can now be determined, the present invention is particularly well suited for determining the soft breakdown of a gate oxide during an in-line process of fabricating a semiconductor device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those who are skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those who are skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.